Area · 2 projects Optional

Chip & EDA

When a check fails, can the agent tell whether the design, the testbench, the constraints or the flow is wrong, and fix that one?

Agents write RTL and circuits, build their own tests, and push designs through implementation tools. Most prior work runs the tests for the agent or repairs one layer at a time. Projects here give the agent control of both the design and how it is checked, and score recovery against the unchanged specification.

Projects

Each project is a direction with room for many kinds of task. Its page says what it asks and what a verifier there should establish.

Design and verification

The agent writes RTL or circuits together with the tests that check them, and debugs failing checks, deciding whether the design, the testbench, the constraints or the properties are wrong.

When a check fails, can the agent tell whether the design or the test is wrong, and fix the right one?

0 tasksOpen the project →

Physical implementation

Take a design from RTL to layout and meet timing, area and power, where the problem may sit in the RTL, the constraints, the floorplan or the flow.

Does the agent close the design at the right layer, without relaxing the targets it was given?

0 tasksOpen the project →

Propose a project

Have a question in Chip & EDA that current benchmarks miss? Propose it as a project: the question, what tasks could look like, and how they could be verified.

opens a GitHub issuePropose →

Tasks in this area